Detailed Product Description
FPGA
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Cyclone FPGA Family
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Description: Stratix II GX devices include 4 to 20 high-speed transceiver channels, each incorporating clock and data recovery unit (CRU) technology and embedded SERDES capability at data rates of up to 6.375 gigabits per second (Gbps).
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Features:
■ Main device features:
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TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to 550 MHz
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Up to 16 global clock networks with up to 32 regional clock networks per device region
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High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
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Up to four enhanced PLLs per device provide spread spectrum, programmable bandwidth, clock switch-over, real-time PLL reconfiguration, and advanced multiplication and phase shifting
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Support for numerous single-ended and differential I/O standards
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High-speed source-synchronous differential I/O support on up to 71 channels.
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Delivery time: 5-7days from distributor
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Payment: T/T in advance
Keywords: Altera FPGA CPLD IC