Detailed Product Description
CPLD
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Programmable Logic Device Family
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Description: The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture.
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Features:
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High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
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5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532
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Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
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Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
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Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)
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5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
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PCI-compliant devices available
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Delivery time: 5-7days from distributor
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Payment: T/T in advance
Keywords: Altera FPGA Altera CPLD
